In designing an integrated circuit, one of the approaches is to perform interactive placement and routing of devices of the integrated circuit. With this design approach, it is desirable to efficiently generate an initial layout of the design so that designers can use that conduct interactive placement and routing of the integrated circuit. Existing EDA tools do not provide adequate support of this design methodology. Some EDA tools, such as the NeoCell AutoPlace from Cadence Design Systems, Inc., use an automatic placement approach to generate the initial layout, which typically takes a long time to run and does not provide a predictable and consistent initial layout. In addition, existing EDA tools do not take into account the locations of the devices in the schematic of the integrated circuit for generating initial layout and thus fail to produce a predictable and consistent initial layout. Furthermore, existing EDA tools do not support user-specified placement constraints for generating initial layout and thus produce initial layouts that do not satisfy users' design requirements.
Therefore, new methods and systems for generating an initial layout of an integrated circuit are needed for addressing the above issues regarding the existing EDA tools.